1. Field
This disclosure relates generally to semiconductor non-volatile memory devices, and more specifically, to a self-aligned in-laid split gate memory and method of making the same.
2. Related Art
In the manufacture of semiconductor non-volatile memory (NVM) devices, various known lithography techniques present serious or difficult gate misalignment control. The techniques also suffer from less scalable integration. In addition, prior manufacturing techniques having included the formation of parasitic control gate (CG) and select gate (SG) structures; however, removal of the parasitic dummy control gate and select gate structures undesirably adds high process complexity and also suffers from scaling limitations. Furthermore, special process steps are required for protecting actual gates and the substrate during removal of the parasitic dummy control and select gate structures. As a result, additional photolithography steps or processes may be required.
Accordingly, there is a need for an improved method and apparatus for overcoming the problems in the art as discussed above.